As a leading technology innovator, we push the boundaries of what's possible and drive transformation in communication and data processing to help create a smarter, connected future for all. In this journey, we are evolving into an “AI-first” intelligent-edge powerhouse, combining high-performance, low-power compute and seamless connectivity while pushing intelligence closer to users through ultra-efficient, on-device AI that ensures privacy, personalization, and real-time responsiveness. This is the Invention Age—and this is where you come in.
Job Overview and Responsibility.
We are seeking a highly skilled engineer to develop 2.5D/3D chiplet and networking solution based on technology-systems co-optimized for a unique era of heterogeneous compute as Moore’s law slows down. The candidate is expected to be an expert in recent technology-architecture trends for heterogeneous low power high performance compute and AI compute. He/she should be able to apply that knowledge to influence the company's’s next generation SoC and platform architectures, including partitions for logic and Cache, DRAM memories, and involving 2.5D/3D chiplets and networking technologies to connect them. Knowledge of emerging optical networking technology is a plus.
Candidate will also drive innovation in the group and across the company's’s product BUs to effectively map emerging AI and other compute use cases to process and chip-integration solutions with detailed knowledge of process technology, 2.5D/3D chiplet architecture, networking technologies, and trade-offs. Knowledge of different IPs (e.g., CPU, GPU, NPU) and how they act together to drive an E2E use case is a plus. Candidate will work with internal architecture and system teams to develop 2.5D/3D partitions and map to 3D stacking topologies. Candidate will perform system KPI analysis to drive 3D architecture and stacking strategies for new product introduction.
Minimum Qualifications:
Additional Qualifications:
Minimum Qualifications